1. Field of the Invention
This invention relates to SDRAM (Synchronized Dynamic Random-Access Memory) technology, and more particularly, to a method of eliminating signal skew in an SDRAM device resulting from the data signal being attenuated into different input signal amplitudes at the respective input points into the memory cells in the SDRAM device.
2. Description of Related Art
The performance of a computer system is dependent on CPU speed as well as memory access speed. Therefore, computer performance can be enhanced by using high-speed memory devices such as DRAM (Dynamic Random-Access Memory). Newer types of DRAMs, such as FPM (Fast Page Mode) DRAM, EDO (Extended Data Out) DRAM, and SDRAM (Synchronized DRAM), can provide very high access speed.
An SDRAM device is typically coupled with an I/O buffer between each memory cell and the signal line. As an SDRAM chip is increased in size to accommodate more transistor elements, it causes an increase in the signal transmission path, thus undesirably resulting in signal skew. This problem is illustratively depicted in the following with reference to FIG. 1.
FIG. 1 is a schematic diagram showing the circuit structure of a conventional SDRAM device. As shown, the SDRAM device includes a plurality of memory cells 11-16 that are connected to a common signal line 18. Each memory cell 11-16 includes an I/O buffer such as an inverter, respectively indicated by the reference numerals 21-26, whose input end is connected to the signal line 18 and whose output end is connected to the internal circuitry of each memory cell. FIG. 3 shows the circuit structure of each of these inverters 21-26, which includes an NMOS transistor 27 and a PMOS transistor 28 and has an input end IN and an output end OUT.
Referring back to FIG. 1, when a data signal S is being transmitted over the signal line 18, it is input into each of the memory cells 11-16 via the respective inverters 21-26. However, the data signal S enters directly into the first memory cell 11, subsequently via an RC circuit (i.e., the resistor R185 and the capacitor C184) into the next memory cell 12, and so forth via an additional RC circuit into the next memory cell until reaching the last memory cell 16.
As a result, the data signal S is attenuated into different input signal amplitudes S1-S6 at the respective input points into the memory cells 11-16; in other words, the first input signal amplitude S1 to the first memory cell 11 is strongest in amplitude, the second input signal amplitude S2 to the next memory cell 12 is reduced in amplitude, and so forth, with the last input signal amplitude S6 to the last memory cell 16 being smallest in amplitude. This causes the enabling signal DL&lt;1&gt; for the first memory cell 11 to be lowest in amplitude and the enabling signal DL&lt;6&gt; for the last memory cell 16 to be largest in amplitude. Since all the inverters 21-26 are set to the same trigger voltage level, the voltages at the respective nodes N1-N6 in the memory cells 11-16 are raised to the trigger voltage level at different times, thus undesirably resulting in signal skew.